In many digital communication systems, phase-locked loop (PLL) circuits are employed in various applications, such as clock synthesis and/or clock or data signal recovery (e.g., from a nonreturn-to-zero (NRZ)-encoded high speed serial data stream). Referring now to FIG. 1, a block schematic diagram shows a conventional PLL circuit 100 using phase detector 104 to compare recovered clock 114 to reference input 102. Phase detector 104 can receive reference input 102 and recovered clock 114 while providing up/down controls 106 to charge pump and filter 108. Variable frequency oscillator (VFO) 112 can receive frequency control 110 from charge pump and filter 108 and may provide recovered clock 114. One drawback of this approach is that the “pull-in range” or the frequency range over which an unlocked PLL may lock to a reference frequency (e.g., reference input 102) is relatively small.
Referring now to FIG. 2, a block schematic diagram shows a conventional PLL circuit 200 having acquisition assist portion 206. Phase detector 204 and acquisition assist 206 can each receive reference input 202 and recovered clock 218. Combining/selecting circuitry 208 can receive signals from phase detector 204 and acquisition assist 206 and may provide up/down controls 210 to charge pump and filter 212. VFO 216 can receive frequency control 214 from charge pump and filter 212 and may provide recovered clock 218. Acquisition assist 206 may operate to effectively widen the pull-in range of PLL 200, as compared to PLL 100 of FIG. 1, for example. However, a combined phase/frequency detector is more desirable for circuit area and overall circuit simplicity than using additional auxiliary circuitry (e.g., acquisition assist 206). But, for PLL applications, such as embedded clock recovery from a serial bit stream (as opposed to the clock synthesizer application shown in FIG. 2), a dedicated or separate phase detector circuit is typically used because there may be essentially no energy at the fundamental data frequency in a high-speed serial data stream (e.g., an NRZ-encoded data stream). A combined phase/frequency detector consistent with such conventional approaches may undesirably lock to an incorrect frequency value.
FIG. 3 shows a block schematic diagram of conventional PLL circuit 300 receiving serial data stream input 302. Phase detector 304 and data sampling and decision circuitry 320 can each receive serial data stream input 302 and recovered clock 318. Data sampling and decision circuitry 320 can provide retimed recovered serial data 322. Frequency detector 306 can receive reference clock input 324 and recovered clock 318. Combining/selecting circuitry 308 can receive signals from phase detector 304 and frequency detector 306 and may provide up/down controls 310 to charge pump and filter 312. VFO 316 can receive frequency control 314 from charge pump and filter 312 and may provide recovered clock 318. In this approach, reference clock input 324 may be generated locally to the PLL and may be used with frequency detector 306 to initially pull-in the PLL. Once PLL lock to reference clock input 324 is achieved, control of the loop frequency may be passed to phase detector 304 (e.g., an Alexander or Hogge style phase detector) which can track transitions in serial data stream input 302. However, a drawback of this approach is increased system cost and complexity due to maintaining a reference clock approximately at the fundamental data frequency of serial data stream input 302.
What is needed is a reliable and simplified pull-in assist mechanism, which does not require a reference clock or an auxiliary frequency detector.